The present invention relates to an internal command generation circuit.
As is well known, a double data rate (DDR) memory device is designed to input or output data in synchronization with both rising and falling edges of a system clock. A DDR memory device operates in a burst mode in order to effectively perform successive read or write operations.
In a burst mode, BL4, BL8, and BL16 are provided. BL4 refers to a mode in which a burst length is set to 4 and 4-bit data are inputted or outputted in response to a single command. BL8 refers to a mode in which a burst length is set to 8 and 8-bit data are inputted or outputted in response to a single command. BL16 refers to a mode in which a burst length is set to 16 and 16-bit data are inputted or outputted in response to a single command.
A DDR memory device uses a prefetch function. Typically, a DDR memory device applies a 2-bit prefetch to input or output 2-bit data successively. A DDR2 memory device applies a 4-bit prefetch to input or output 4-bit data successively.
In a read or write operation, a semiconductor memory device generates an internal command whose pulse number is determined depending on a set burst mode. More specifically when a burst mode is set to BL4, an internal command having no pulse is generated. When a burst mode is set to BL8, an internal command having one pulse is generated. When a burst mode is set to BL16, an internal command having three pulses is generated.
This is because when a read or write command is inputted for a read or write operation in a DDR2 memory device to which a 4-bit prefetch is applied, 4-bit data are basically inputted or outputted successively, and 4-bit data are inputted or outputted successively whenever a pulse of an internal command is generated.